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Date
Dec. 10. 2002
32M (x16) Flash Memory
LH28F320BFE-PTTL60
LHF32FB1
* Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. * When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * Office electronics * Instrumentation and measuring equipment * Machine tools * Audiovisual equipment * Home appliance * Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * Aerospace equipment * Communications equipment for trunk lines * Control equipment for the nuclear power industry * Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. * Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 2.44
LHF32FB1
1
CONTENTS
PAGE 48-Lead TSOP Pinout................................................. 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with Four Planes .................................. 5 Memory Map .............................................................. 6
PAGE Extended Status Register Definition ......................... 15 Partition Configuration Register Definition.............. 16 Partition Configuration ............................................. 16 1 Electrical Specifications......................................... 17 1.1 Absolute Maximum Ratings ........................... 17
Identifier Codes and OTP Address for Read Operation ............................................. 7 Identifier Codes and OTP Address for Read Operation on Partition Configuration........ 7 OTP Block Address Map for OTP Program............... 8
1.2 Operating Conditions ...................................... 17 1.2.1 Capacitance .............................................. 18 1.2.2 AC Input/Output Test Conditions ............ 18 1.2.3 DC Characteristics ................................... 19
Bus Operation............................................................. 9 Command Definitions .............................................. 10 Functions of Block Lock and Block Lock-Down..... 12 Block Locking State Transitions upon Command Write................................................ 12 Block Locking State Transitions upon WP#/ACC Transition ....................................... 13 Status Register Definition......................................... 14 2 Related Document Information.............................. 29 1.2.4 AC Characteristics - Read-Only Operations......................... 21 1.2.5 AC Characteristics - Write Operations ................................. 25 1.2.6 Reset Operations ...................................... 27 1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance.................... 28
Rev. 2.44
LHF32FB1
2
LH28F320BFE-PTTL60 32Mbit (2Mbitx16) Page Mode Dual Work Flash MEMORY
32M density with 16Bit I/O Interface High Performance Reads * 60/25ns 8-Word Page Mode Configurative 4-Plane Dual Work * Flexible Partitioning * Read operations during Block Erase or (Page Buffer) Program * Status Register for Each Partition Low Power Operation * 2.7V Read and Write Operations * Automatic Power Savings Mode Reduces ICCR in Static Mode Enhanced Code + Data Storage * 5s Typical Erase/Program Suspends OTP (One Time Program) Block * 4-Word Factory-Programmed Area * 4-Word User-Programmable Area High Performance Program with Page Buffer * 16-Word Page Buffer * 5s/Word (Typ.) at 12V WP#/ACC Operating Temperature 0C to +70C CMOS Process (P-type silicon substrate) Flexible Blocking Architecture * Eight 4K-word Parameter Blocks * Sixty-three 32K-word Main Blocks * Top Parameter Location Enhanced Data Protection Features * Individual Block Lock and Block Lock-Down with Zero-Latency * All blocks are locked at power-up or device reset. * Block Erase, Full Chip Erase, (Page Buffer) Word Program Lockout during Power Transitions Automated Erase/Program Algorithms * 3.0V Low-Power 11s/Word (Typ.) Programming * 12V No Glue Logic 9s/Word (Typ.) Production Programming and 0.5s Erase (Typ.) Cross-Compatible Command Support * Basic Command Set * Common Flash Interface (CFI) Extended Cycling Capability * Minimum 100,000 Block Erase Cycles 48-Lead TSOP ETOXTM* Flash Technology Not designed or rated as radiation hardened
The product, which is 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can operate at VCC=2.7V-3.6V. Its low voltage operation capability greatly extends battery life for portable applications. The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual work operation. The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and data storage. Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP (One Time Program) block provides an area to store permanent code such as a unique number. * ETOX is a trademark of Intel Corporation.
Rev. 2.44
LHF32FB1
3
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-LEAD TSOP STANDARD PINOUT 12mm x 20mm TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 NC GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0
Figure 1. 48-Lead TSOP (Normal Bend) Pinout
Rev. 2.44
LHF32FB1
4
Table 1. Pin Descriptions Symbol A0-A20 Type INPUT INPUT/ OUTPUT Name and Function ADDRESS INPUTS: Inputs for addresses. 32M: A0-A20 DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, identifier code and partition configuration register code reads. Data pins float to highimpedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to standby levels. RESET: When low (VIL), RST# resets internal automation and inhibits write operations which provides data protection. RST#-high (VIH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. RST# must be low during power-up/down. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of CE# or WE# (whichever goes high first). WRITE PROTECT: When WP#/ACC is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and not locked-down. When WP#/ACC is VIH, lock-down is disabled. Applying 12V0.3V to WP#/ACC provides fast erasing or fast programming mode. In this mode, WP#/ACC is power supply pin. Applying 12V0.3V to WP#/ACC during erase/program can only be done for a maximum of 1,000 cycles on each block. WP#/ ACC may be connected to 12V0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits may reduce block cycling capability or cause permanent damage.
DQ0-DQ15
CE#
INPUT
RST#
INPUT
OE# WE#
INPUT INPUT
WP#/ACC
INPUT/ SUPPLY
RY/BY#
READY/BUSY#: Indicates the status of the internal WSM (Write State Machine). When OPEN DRAIN low, WSM is performing an internal operation (block erase, full chip erase, (page buffer) program or OTP program). RY/BY#-High Z indicates that the WSM is ready for new OUTPUT commands, block erase is suspended and (page buffer) program is inactive, (page buffer) program is suspended, or the device is in reset mode. SUPPLY SUPPLY DEVICE POWER SUPPLY (2.7V-3.6V): With VCCVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated.
VCC GND NC
Rev. 2.44
LHF32FB1
5
Table 2. Simultaneous Operation Modes Allowed with Four Planes(1, 2) THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS: Read Array Read ID/OTP Read Status Read Query Word Program Page Buffer Program OTP Program Block Erase Full Chip Erase Program Suspend Block Erase Suspend X X X X X X Read Read Read Array ID/OTP Status X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Read Word Query Program X X X X X X X X X X Page Block OTP Block Full Chip Program Buffer Erase Program Erase Erase Suspend Program Suspend X X X X X X X X X X X X X X X X X X X X
NOTES: 1. "X" denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing. Commands must be written to an address within the block targeted by that command.
Rev. 2.44
LHF32FB1
6
BLOCK NUMBER ADDRESS RANGE
70 69 68 67 66 65 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 1FF000H - 1FFFFFH 1FE000H - 1FEFFFH 1FD000H - 1FDFFFH 1FC000H - 1FCFFFH 1FB000H - 1FBFFFH 1FA000H - 1FAFFFH 1F9000H - 1F9FFFH 1F8000H - 1F8FFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH
PLANE3 (PARAMETER PLANE)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
BLOCK NUMBER ADDRESS RANGE
31 32K-WORD 30 32K-WORD 29 32K-WORD 28 32K-WORD 0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH
PLANE1 (UNIFORM PLANE)
1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH
27 32K-WORD 26 32K-WORD 25 32K-WORD 24 32K-WORD 23 32K-WORD 22 32K-WORD 21 32K-WORD 20 32K-WORD 19 32K-WORD 18 32K-WORD 17 32K-WORD 16 32K-WORD
47 46 45 44
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH
15 32K-WORD 14 32K-WORD 13 32K-WORD 12 32K-WORD
078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 000000H - 007FFFH
PLANE2 (UNIFORM PLANE)
43 42 41 40 39 38 37 36 35 34 33 32
PLANE0 (UNIFORM PLANE)
158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH
11 32K-WORD 10 32K-WORD 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
Figure 2. Memory Map (Top Parameter)
Rev. 2.44
LHF32FB1
7
Table 3. Identifier Codes and OTP Address for Read Operation Code Manufacturer Code Device Code Block Lock Configuration Code Manufacturer Code Top Parameter Device Code Block is Unlocked Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code OTP Partition Configuration Register OTP Lock OTP 0006H 0080H 0081-0088H Block Address +2 Address [A15-A0] 0000H 0001H Data [DQ15-DQ0] 00B0H 00B4H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 PCRC OTP-LK OTP Notes 1 1, 2 3 3 3 3 1, 4 1, 5 1, 6
NOTES: 1. The address A20-A16 are shown in below table for reading the manufacturer code, device code, device configuration code and OTP data. 2. Top parameter device has its parameter blocks in the plane3 (The highest address). 3. Block Address = The beginning location of a block address within the partition to which the Read Identifier Codes/OTP command (90H) has been written. DQ15-DQ2 are reserved for future implementation. 4. PCRC=Partition Configuration Register Code. 5. OTP-LK=OTP Block Lock configuration. 6. OTP=OTP Block data.
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) (32M-bit device) Partition Configuration Register (2) PCR.10 0 0 0 1 0 1 1 1 PCR.9 0 0 1 0 1 1 0 1 PCR.8 0 1 0 0 1 0 1 1 00H 00H or 08H 00H or 10H 00H or 18H 00H or 08H or 10H 00H or 10H or 18H 00H or 08H or 18H 00H or 08H or 10H or 18H Address (32M-bit device) [A20-A16]
NOTES: 1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read Identifier Codes/OTP command (90H). 2. Refer to Table 12 for the partition configuration register.
Rev. 2.44
LHF32FB1
8
[A20-A0] 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H 000080H
Reserved for Future Implementation (DQ15-DQ2)
Customer Programmable Area Lock Bit (DQ1) Factory Programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.)
Rev. 2.44
LHF32FB1
9
Table 5. Bus Operation(1, 2) Mode Read Array Output Disable Standby Reset Read Identifier Codes/OTP Read Query Write 3 6 Notes 6 RST# VIH VIH VIH VIL VIH VIH VIH CE# VIL VIL VIH X VIL VIL VIL OE# VIL VIH X X VIL VIL VIH WE# VIH VIH X X VIH VIH VIL Address X X X X DQ0-15 DOUT High Z High Z High Z RY/BY# (8) X X X High Z X
See See Table 3 and Table 3 and Table 4 Table 4 See Appendix X See Appendix DIN
6,7 4,5,6
X X
NOTES: 1. See DC Characteristics for VIL or VIH voltages. 2. X can be VIL or VIH. 3. RST# at GND0.2V ensures the lowest power consumption. 4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when VCC=2.7V-3.6V. 5. Refer to Table 6 for valid DIN during a write operation. 6. Never hold OE# low and WE# low at the same timing. 7. Refer to Appendix of LH28F320BF series for more information about query code. 8. RY/BY# is VOL when the WSM (Write State Machine) is executing internal block erase, full chip erase, (page buffer) program or OTP program algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with program and page buffer program inactive), (page buffer) program suspend mode, or reset mode.
Rev. 2.44
LHF32FB1
10
Table 6. Command Definitions(11) Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit OTP Program Set Partition Configuration Register Bus Cycles Req'd 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 2 9 10 5 5,9 5,6 5,7 8,9 8,9 4 4 First Bus Cycle Notes Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr(2) PA PA PA PA PA BA X WA WA PA PA BA BA BA OA PCRC Data FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H C0H 60H Write Write Write Write Write BA BA BA OA PCRC 01H D0H 2FH OD 04H Write Write Write Write BA X WA WA D0H D0H WD N-1 Read Read Read IA or OA QA PA ID or OD QD SRD Second Bus Cycle Oper(1) Addr(2) Data(3)
NOTES: 1. Bus operations are defined in Table 5. 2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. X=Any valid address within the device. PA=Address within the selected partition. IA=Identifier codes address (See Table 3 and Table 4). QA=Query codes address. Refer to Appendix of LH28F320BF series for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. OA=Address of OTP block to be read or programmed (See Figure 3). PCRC=Partition configuration register code presented on the address A0-A15. 3. ID=Data read from identifier codes. (See Table 3 and Table 4). QD=Data read from query database. Refer to Appendix of LH28F320BF series for details. SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles. OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles. N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST# is VIH.
Rev. 2.44
LHF32FB1
11
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of LH28F320BF series for details. 8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while the block erase operation is being suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP#/ACC is VIL. When WP#/ACC is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
Rev. 2.44
LHF32FB1
12
Table 7. Functions of Block Lock(5) and Block Lock-Down Current State State [000] [001](3) [011] [100] [101](3) [110](4) [111] WP#/ACC 0 0 0 1 1 1 1 DQ1(1) 0 0 1 0 0 1 1 DQ0(1) 0 1 1 0 1 0 1 State Name Unlocked Locked Locked-down Unlocked Locked Lock-down Disable Lock-down Disable Erase/Program Allowed (2) Yes No No Yes No Yes No
NOTES: 1. DQ0=1: a block is locked; DQ0=0: a block is unlocked. DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down. 2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (WP#/ACC=0) or [101] (WP#/ACC=1), regardless of the states before power-off or reset operation. 4. When WP#/ACC is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 5. OTP (One Time Program) block has the lock function which is different from those described above.
Table 8. Block Locking State Transitions upon Command Write(4) Current State State [000] [001] [011] [100] [101] [110] [111] WP#/ACC 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after Lock Command Written (Next State) Set Lock(1) [001] No Change(3) No Change [101] No Change [111] No Change Clear Lock(1) No Change [000] No Change No Change [100] No Change [110] Set Lock-down(1) [011](2) [011] No Change [111](2) [111] [111](2) No Change
NOTES: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that WP#/ACC is not changed and fixed VIL or VIH.
Rev. 2.44
LHF32FB1
13
Table 9. Block Locking State Transitions upon WP#/ACC Transition(4) Current State Previous State State [110](2) Other than [110](2) [100] [101] [110] [111] 1 1 1 1 0 0 1 1 0 1 0 1 [000] [001] [011] WP#/ACC 0 0 0 DQ1 0 0 1 DQ0 0 1 1 Result after WP#/ACC Transition (Next State) WP#/ACC=01(1) WP#/ACC=10(1) [100] [101] [110] [111] [000] [001] [011](3) [011]
NOTES: 1. "WP#/ACC=01" means that WP#/ACC is driven to VIH and "WP#/ACC=10" means that WP#/ACC is driven to VIL. 2. State transition from the current state [011] to the next state depends on the previous state. 3. When WP#/ACC is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.
Rev. 2.44
LHF32FB1
14
Table 10. Status Register Definition R 15 WSMS 7 R 14 BESS 6 R 13 BEFCES 5 R 12 PBPOPS 4 R 11 WPACCS 3 R 10 PBPSS 2 NOTES: R 9 DPS 1 R 8 R 0
SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM STATUS (PBPOPS) 1 = Error in (Page Buffer) Program or OTP Program 0 = Successful (Page Buffer) Program or OTP Program SR.3 = WP#/ACC STATUS (WPACCS) 1 = VCC+0.4V < WP#/ACC < 11.7V Detect, Operation Abort 0 = WP#/ACC OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. Check SR.7 or RY/BY# to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.1 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, set partition configuration register attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of WP#/ACC level. The WSM interrogates and indicates the WP#/ACC level only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. SR.3 is not guaranteed to report accurate feedback when WP#/ ACCVACCH. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status. SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register.
Rev. 2.44
LHF32FB1
15
Table 11. Extended Status Register Definition R 15 SMS 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 R 10 R 2 R 9 R 1 R 8 R 0
XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available
NOTES: After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) register.
Rev. 2.44
LHF32FB1
16
Table 12. Partition Configuration Register Definition R 15 R 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 PC2 10 R 2 PC1 9 R 1 PC0 8 R 0
PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. 100 = Plane 0-2 are merged into one partition. (default in a top parameter device) 011 = Plane 2-3 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 110 = Plane 0-1 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 101 = Plane 1-2 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions.
PC2 PC1PC0
111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions. PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTES: After power-up or device reset, PCR10-8 (PC2-0) is set to "001" in a bottom parameter device and "100" in a top parameter device. See Figure 4 for the detail on partition configuration. PCR.15-11 and PCR.7-0 are reserved for future use and should be masked out when checking the partition configuration register.
PC2 PC1PC0
PARTITIONING FOR DUAL WORK PARTITION0
PLANE3 PLANE2 PLANE1 PLANE0
PARTITIONING FOR DUAL WORK PARTITION2 PARTITION1 PARTITION0
PLANE3 PLANE2 PLANE1 PLANE0
000
011
PARTITION1
PLANE3 PLANE2 PLANE1
PARTITION0
PLANE0
PARTITION2 PARTITION1 PARTITION0
PLANE3 PLANE2 PLANE1
001
110
PARTITION1
PLANE3 PLANE2
PARTITION0
PLANE1 PLANE0
PARTITION2 PARTITION1 PARTITION0
PLANE3 PLANE2 PLANE1
010
101
PARTITION1
PLANE3 PLANE2
PARTITION0
PLANE1 PLANE0
PARTITION3 PARTITION2 PARTITION1 PARTITION0
PLANE3
PLANE2
PLANE1
100
111
Figure 4. Partition Configuration
Rev. 2.44
PLANE0
PLANE0
PLANE0
LHF32FB1 1 Electrical Specifications 1.1 Absolute Maximum Ratings*
Operating Temperature During Read, Erase and Program ...... 0C to +70C (1) Storage Temperature During under Bias............................... -10C to +80C During non Bias................................ -65C to +125C Voltage On Any Pin (except VCC and WP#/ACC)... -0.5V to VCC+0.5V (2) VCC Supply Voltage ........................... -0.2V to +3.9V (2) WP#/ACC Supply Voltage ......... -0.2V to +12.6V (2, 3, 4) Output Short Circuit Current ........................... 100mA (5)
17
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC and WP#/ACC pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 3. Maximum DC voltage on WP#/ACC may overshoot to +13.0V for periods <20ns. 4. WP#/ACC erase/program voltage is normally 2.7V3.6V. Applying 11.7V-12.3V to WP#/ACC during erase/program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. WP#/ACC may be connected to 11.7V-12.3V for a total of 80 hours maximum. 5. Output shorted for no more than one second. No more than one output shorted at a time.
1.2 Operating Conditions
Parameter Operating Temperature VCC Supply Voltage WP#/ACC Voltage when Used as a Logic Control VIH WP#/ACC Supply Voltage Main Block Erase Cycling: WP#/ACC=VIL or VIH Parameter Block Erase Cycling: WP#/ACC=VIL or VIH Main Block Erase Cycling: WP#/ACC=VACCH, 80 hrs. Parameter Block Erase Cycling: WP#/ACC=VACCH, 80 hrs. Maximum WP#/ACC hours at VACCH VACCH 2.4 11.7 100,000 100,000 1,000 1,000 80 12 Symbol TA VCC VIL Min. 0 2.7 -0.4 Typ. +25 3.0 Max. +70 3.6 0.4 VCC + 0.4 12.3 Unit C V V V V Cycles Cycles Cycles Cycles Hours 1 1, 2 1 Notes
NOTES: 1. See DC Characteristics tables for voltage range-specific specification. 2. Applying WP#/ACC=11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. A permanent connection to WP#/ACC=11.7V-12.3V is not allowed and can cause damage to the device.
Rev. 2.44
LHF32FB1
18
1.2.1 Capacitance(1) (TA=+25C, f=1MHz)
Parameter Input Capacitance WP#/ACC Input Capacitance Output Capacitance NOTE: 1. Sampled, not 100% tested. Symbol CIN CIN COUT Condition VIN=0.0V VIN=0.0V VOUT=0.0V Min. Typ. 4 18 6 Max. 7 22 10 Unit pF pF pF
1.2.2 AC Input/Output Test Conditions
VCC INPUT 0.0 AC test inputs are driven at VCC(min) for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends at VCC/2. Input rise and fall times (10% to 90%) < 5ns. Worst case speed conditions are when VCC=VCC(min). VCC/2 TEST POINTS VCC/2 OUTPUT
Figure 5. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
Table 13. Configuration Capacitance Loading Value
VCC(min)/2
1N914
RL=3.3k DEVICE UNDER TEST CL Includes Jig Capacitances. CL OUT
Test Configuration VCC=2.7V-3.6V
CL (pF) 50
Figure 6. Transient Equivalent Testing Load Circuit
Rev. 2.44
LHF32FB1 1.2.3 DC Characteristics
VCC=2.7V-3.6V Symbol ILI ILO Parameter Input Load Current Output Leakage Current Notes 1 1 Min. -1.0 -1.0 Typ. Max. +1.0 +1.0 Unit A A
19
Test Conditions VCC=VCCMax., VIN/VOUT=VCC or GND VCC=VCCMax., CE#=RST#= VCC0.2V, WP#/ACC=VCC or GND VCC=VCCMax., CE#=GND0.2V, WP#/ACC=VCC or GND RST#=GND0.2V VCC=VCCMax., CE#=VIL, OE#=VIH, f=5MHz WP#/ACC=VIL or VIH WP#/ACC=VACCH WP#/ACC=VIL or VIH WP#/ACC=VACCH CE#=VIH WP#/ACCVCC WP#/ACC=VIL or VIH WP#/ACC=VACCH WP#/ACC=VIL or VIH WP#/ACC=VACCH WP#/ACC=VIL or VIH WP#/ACC=VACCH WP#/ACC=VIL or VIH WP#/ACC=VACCH
ICCS
VCC Standby Current
1,7
4
20
A
ICCAS
VCC Automatic Power Savings Current
1,3
4
20
A A mA
ICCD
VCC Reset Power-Down Current Average VCC Read Current Normal Mode Average VCC Read 8 Word Read Current Page Mode VCC (Page Buffer) Program Current VCC Block Erase, Full Chip Erase Current VCC (Page Buffer) Program or Block Erase Suspend Current WP#/ACC Standby or Read Current WP#/ACC Current (Page Buffer)
1 1,6
4 15
20 25
ICCR
1,6 1,4,6 1,4,6 1,4,6 1,4,6 1,2,6 1,5,6
5 20 10 10 4 10 2 2 10 2 5 2 10 2 10
10 60 20 30 10 200 5 5 30 5 15 5 200 5 200
mA mA mA mA mA A A A mA A mA A A A A
ICCW ICCE ICCWS ICCES IACCS IACCR IACCW IACCE IACCWS IACCES
Program 1,4,5,6 1,4,5,6 1,4,5,6 1,4,5,6 1,5,6 1,5,6
WP#/ACC Block Erase, Full Chip Erase Current WP#/ACC (Page Buffer) Program Suspend Current WP#/ACC Current Block Erase
Suspend 1,5,6 1,5,6
Rev. 2.44
LHF32FB1
20
DC Characteristics (Continued) VCC=2.7V-3.6V Symbol VIL VIH VOL VOH VACCH VLKO Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage WP#/ACC during Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program Operations VCC Lockout Voltage Notes 4 4 4,7 4 VCC -0.2 11.7 1.5 12 12.3 Min. -0.4 2.4 Typ. Max. 0.4 VCC + 0.4 0.2 Unit V V V V VCC=VCCMin., IOL=100A VCC=VCCMin., IOH=-100A Test Conditions
5
V V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V and TA=+25C unless VCC is specified. 2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase suspend mode, the device's current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page buffer) program suspend mode, the device's current draw is the sum of ICCWS and ICCR. 3. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 4. Sampled, not 100% tested. 5. Applying 12V0.3V to WP#/ACC provides fast erasing or fast programming mode. In this mode, WP#/ACC is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the VCC power bus. Applying 12V0.3V to WP#/ACC during erase/program can only be done for a maximum of 1,000 cycles on each block. WP#/ACC may be connected to 12V0.3V for a total of 80 hours maximum. 6. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane. 7. Includes RY/BY#.
Rev. 2.44
LHF32FB1 1.2.4 AC Characteristics - Read-Only Operations(1)
VCC=2.7V-3.6V, TA=0C to +70C Symbol tAVAV tAVQV tELQV tAPA tGLQV tPHQV tEHQZ, tGHQZ tELQX tGLQX tOH tAVEL, tAVGL tELAX, tGLAX tEHEL, tGHGL Read Cycle Time Address to Output Delay CE# to Output Delay Page Address Access Time OE# to Output Delay RST# High to Output Delay CE# or OE# to Output in High Z, Whichever Occurs First CE# to Output in Low Z OE# to Output in Low Z Output Hold from First Occurring Address, CE# or OE# change Address Setup to CE#, OE# Going Low for Reading Status Register Address Hold from CE#, OE# Going Low for Reading Status Register CE#, OE# Pulse Width High for Reading Status Register 2 2 2 2 4, 6 5, 6 6 0 0 0 10 30 15 3 3 Parameter Notes Min. 60 60 60 25 20 150 20 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
21
NOTES: 1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. Sampled, not 100% tested. 3. OE# may be delayed up to tELQV tGLQV after the falling edge of CE# without impact to tELQV. 4. Address setup time (tAVEL, tAVGL) is defined from the falling edge of CE# or OE# (whichever goes low last). 5. Address hold time (tELAX, tGLAX) is defined from the falling edge of CE# or OE# (whichever goes low last). 6. Specifications tAVEL, tAVGL, tELAX, tGLAX and tEHEL, tGHGL for read operations apply to only status register read operations.
Rev. 2.44
LHF32FB1
22
A20-0 (A)
VIH VIL tAVQV tEHEL
VALID ADDRESS tAVAV tEHQZ tGHQZ
CE# (E)
VIH VIL tAVEL tAVGL tGHGL VIH VIL tELQV tGLAX tELAX
OE# (G)
WE# (W)
VIH VIL tGLQV tGLQX tELQX tOH tOH VALID OUTPUT tPHQV
DQ15-0 (D/Q)
VOH VOL
High Z
RST# (P)
VIH VIL
Figure 7. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 2.44
LHF32FB1
23
A20-3 (A)
VIH VIL
VALID ADDRESS tAVAV tAVQV
A2-0 (A)
VIH VIL
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
CE# (E)
VIH VIL tELQV tEHQZ tGHQZ
OE# (G)
VIH VIL
WE# (W)
VIH VIL tGLQX tELQX tAPA tOH tGLQV
DQ15-0 (D/Q)
VOH VOL
High Z
tPHQV
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
RST# (P)
VIH VIL
Figure 8. AC Waveform for Asynchronous 4-Word Page Mode Read Operations from Main Blocks or Parameter Blocks
Rev. 2.44
LHF32FB1
24
A20-3 (A)
VIH VIL
VALID ADDRESS tAVAV tAVQV
A2-0 (A)
VIH VIL
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
CE# (E)
VIH VIL tELQV tEHQZ tGHQZ
OE# (G)
VIH VIL
WE# (W)
VIH VIL tGLQX tELQX tAPA tOH tGLQV
DQ15-0 (D/Q)
VOH VOL
High Z
tPHQV
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
RST# (P)
VIH VIL
Figure 9. AC Waveform for Asynchronous 8-Word Page Mode Read Operations from Main Blocks or Parameter Blocks
Rev. 2.44
LHF32FB1 1.2.5 AC Characteristics - Write Operations(1), (2)
VCC=2.7V-3.6V, TA=0C to +70C Symbol tAVAV tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tSHWH (tSHEH) tWHGL (tEHGL) tQVSL tWHR0 (tEHR0) tWHRL (tEHRL) Write Cycle Time RST# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold from WE# (CE#) High Data Hold from WE# (CE#) High Address Hold from WE# (CE#) High WE# (CE#) Pulse Width High WP#/ACC High Setup to WE# (CE#) WP#/ACC=VIH Going High WP#/ACC=VACCH Write Recovery before Read WP#/ACC High Hold from Valid SRD, RY/BY# High Z WE# (CE#) High to SR.7 Going "0" WE# (CE#) High to RY/BY# Going Low 3 3, 6 3 5 3 4 7 7 3 Parameter Notes Min. 60 150 0 45 40 45 0 0 0 15 0 200 30 0 tAVQV +50 100 Max.
25
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. 5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns. 7. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration.
Rev. 2.44
LHF32FB1
26
NOTE 1 A20-0 (A)
VIH VIL
NOTE 2
VALID ADDRESS tAVAV
NOTE 3
VALID ADDRESS tAVWH (tAVEH)
NOTE 4
VALID ADDRESS
NOTE 5
CE# (E)
VIH VIL tELWL (tWLEL) tWHEH (tEHWH)
tWHAX (tEHAX)
NOTES 5, 6
tWHGL (tEHGL)
OE# (G)
VIH VIL tPHWL (tPHEL) VIH VIL tWLWH (tELEH ) tWHQV1,2,3 (tEHQV1,2,3) tWHDX (tEHDX) tDVWH (tDVEH) tWHWL (tEHEL)
NOTES 5, 6
WE# (W)
DQ15-0 (D/Q)
VIH VIL DATA IN DATA IN tWHRL (tEHRL) (tWHR0 (tEHR0))
VALID SRD
High Z
RY/BY# ("1") (R) (SR.7) VOL
("0")
RST# (P)
VIH VIL tSHWH (tSHEH) tQVSL
WP#/ACC (S) WP# (S)
VIH, VACCH IH VIL
NOTES: 1. VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.
Figure 10. AC Waveform for Write Operations
Rev. 2.44
LHF32FB1 1.2.6 Reset Operations
tPHQV RST#
(P)
27
VIH VIL
High Z
tPLPH
VALID OUTPUT
V DQ15-0 (D/Q) OH VOL
(A) Reset during Read Array Mode
ABORT COMPLETE
SR.7="1"
tPLRH RST#
(P)
tPHQV
VIH VIL
High Z
tPLPH
VALID OUTPUT
V DQ15-0 (D/Q) OH VOL VCC(min) GND
(B) Reset during Erase or Program Mode
VCC
tVHQV t2VPH tPHQV
RST#
(P)
VIH VIL
High Z
VALID OUTPUT
V DQ15-0 (D/Q) OH VOL
(C) RST# rising timing
Figure 11. AC Waveform for Reset Operations Reset AC Specifications (VCC=2.7V-3.6V, TA=0C to +70C)
Symbol tPLPH tPLRH t2VPH tVHQV
Parameter RST# Low to Reset during Read (RST# should be low during power-up.) RST# Low to Reset during Erase or Program VCC 2.7V to RST# High VCC 2.7V to Output Delay
Notes 1, 2, 3 1, 3, 4 1, 3, 5 3
Min. 100
Max.
Unit ns
22 100 1
s ns ms
NOTES: 1. A reset time, tPHQV, is required from the later of SR.7 (RY/BY#) going "1" (High Z) or RST# going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for tPHQV. 2. tPLPH is <100ns the device may still reset but this is not guaranteed. 3. Sampled, not 100% tested. 4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and also has been in stable there.
Rev. 2.44
LHF32FB1
28
1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3)
VCC=2.7V-3.6V, TA=0C to +70C Page Buffer WP#/ACC=VIL or VIH WP#/ACC=VACCH Command is (In System) (In Manufacturing) Unit Notes Used or not (1) (2) Min. (1) (2) Min. Typ. Max. Typ. Max. Used 2 2 2 2 2 2 2 2 2 2 4 4 Not Used Used Not Used Used Not Used Used Not Used 0.05 0.03 0.38 0.24 11 7 36 0.3 0.6 40 5 5 0.3 0.12 2.4 1.0 200 100 400 4 5 350 10 20 0.04 0.02 0.31 0.17 9 5 27 0.2 0.5 33 5 5 0.12 0.06 1.0 0.5 185 90 185 4 5 350 10 20 s s s s s s s s s s s s s
Symbol
Parameter
tWPB tWMB tWHQV1/ tEHQV1 tWHOV1/ tEHOV1 tWHQV2/ tEHQV2 tWHQV3/ tEHQV3 tWHRH1/ tEHRH1 tWHRH2/ tEHRH2 tERES
4K-Word Parameter Block Program Time 32K-Word Main Block Program Time Word Program Time OTP Program Time 4K-Word Parameter Block Erase Time 32K-Word Main Block Erase Time Full Chip Erase Time (Page Buffer) Program Suspend Latency Time to Read Block Erase Suspend Latency Time to Read Latency Time from Block Erase Resume Command to Block Erase Suspend Command
5
-
500
500
NOTES: 1. Typical values measured at VCC=3.0V, WP#/ACC=3.0V or 12V, and TA=+25C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1" or RY/BY# going High Z. 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished.
Rev. 2.44
LHF32FB1 2 Related Document Information(1)
Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. Document Name LH28F320BF series Appendix
29
Rev. 2.44
i
LH28F320BFXX-XXXXXX Flash MEMORY ERRATA
1. AC Characteristics
PROBLEM The table below summarizes the AC characteristics. AC Characteristics - Write Operations
VCC=2.7V-3.6V Page 25 25 25 tAVAV tWLWH (tELEH) tWHWL (tEHEL) Symbol Write Cycle Time WE# (CE#) Pulse Width WE# (CE#) Pulse Width High tAVAV=75ns Parameter Min. 75 50 25 Max. Unit ns ns ns
WORKAROUND System designers should consider these specifications. STATUS This is intended to be fixed in future devices.
021114
i
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VCC(min) VCC GND VIH RP# (P) (RST#) ADDRESS (A) VIL tF VIH CE#
(E)
tVR
t2VPH
tPHQV
VIL tR or tF VIH tAVQV Valid Address tELQV
tR or tF
tR
VIL VIH WE# (W) VIL tF VIH OE#
(G)
tGLQV
tR
VIL DATA VOH VOL High Z Valid Output
(D/Q)
Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol tVR tR tF VCC Rise Time
Parameter
Notes 1 1, 2 1, 2
Min. 0.5
Max. 30000 1 1
Unit s/V s/V s/V
Input Signal Rise Time Input Signal Fall Time
NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations.
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal VIH (Min.)
Input Signal VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E
Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, VPP Electric Potential Switching Circuit
NOTE: 1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
v A-3 STATUS REGISTER READ OPERATIONS
If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit SR.15 instead of SR.7 to determine when the erase or program operation has been completed. Table A-3-1. Status Register Definition (SR.15 and SR.7) NOTES: SR.15 = WRITE STATE MACHINE STATUS: (DQ15) 1 = Ready in All Partitions 0 = Busy in Any Partition SR.7 = WRITE STATE MACHINE STATUS FOR EACH PARTITION: (DQ 7) 1 = Ready in the Addressed Partition 0 = Busy in the Addressed Partition SR.15 indicates the status of WSM (Write State Machine). If SR.15="0", erase or program operation is in progress in any partition. SR.7 indicates the status of the partition. If SR.7="0", erase or program operation is in progress in the addressed partition. Even if the SR.7 is "1", the WSM may be occupied by the other partition.
Operation to Partition 0
Address (A) CE# (E) WE# (W) DQ15-0 (D/Q) SR.15 (R) ( Partition 0 ) SR.7 (R) ( Partition 0 ) SR.15 (R) ( Partition 1 ) SR.7 (R) ( Partition 1 ) SR.15 (R) ( Partition 2 ) SR.7 (R) ( Partition 2 ) SR.15 (R) ( Partition 3 ) SR.7 (R) ( Partition 3 )
VIH VIL VIH VIL VIH VIL VIH VIL "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" tWHR0 (tEHR0) VALID COMMAND VALID ADDRESS within PARTITION 0
Operation to Partition 2
VALID ADDRESS within PARTITION 2
VALID COMMAND tWHR0 (tEHR0)
PARTITION3 PARTITION2 PARTITION1 PARTITION0
PLANE3 PLANE2 PLANE1 PLANE0
Check SR.15 instead of SR.7 in Partition 0
Check SR.15 instead of SR.7 in Partition 2
Figure A-3-1. Example of Checking the Status Register (In this example, the device contains four partitions.) 021211

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